🔁 Cache Coherence - hello · Scour

SplittingSecrets: A Compiler-Based Defense for Preventing Data Memory-Dependent Prefetcher Side-Channels

arxiv.org·15h

🚀Software Prefetching

One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon

riscv.org·46m

Scalable Adaptive Memory Compiler Optimization via Multi-Objective Evolutionary Algorithms

dev.to·17h·

Discuss: DEV

SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads

danglingpointers.substack.com·1d·

Discuss: Substack

🧵Lightweight Threads

Context Discipline and Performance Correlation: Analyzing LLM Performance and Quality Degradation Under Varying Context Lengths

arxiv.org·15h

🔗Link-Time Optimization

ANN v3: 200ms p99 query latency over 100 billion vectors

turbopuffer.com·20h·

Discuss: Hacker News

🌊Memory Bandwidth

Memory Addressing and Memory Mapped I/O | by Tom Herbert | Jan, 2026

medium.com·2d

FlashAttention 4: Faster, Memory-Efficient Attention for LLMs

digitalocean.com·8h

🔄Hardware Transactional Memory

Computer-on-Modules for an efficient entry into rugged embedded edge AI applications

einpresswire.com·1d

🔌Embedded Systems

Node.js 16 to 25 Benchmarks: How Performance Evolved Over Time

repoflow.io·1d·

Discuss: r/node

A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)

semiengineering.com·1h

🔄Hardware Transactional Memory

Lock Management Inside a Process: Why Native Locks Alone Are Not Enough

dev.to·52m·

Discuss: DEV

Intrinsic back-switching phenomenon in spin-orbit torque MRAM devices

link.aps.org·12h

🔄Hardware Transactional Memory

Every Mini PC & SFF Hardware Announced at CES 2026

williamlam.com·5h

Heaps do lie: debugging a memory leak in vLLM.

mistral.ai·5h·

Discuss: Hacker News

Shared execution plan cache for Amazon Aurora PostgreSQL

aws.amazon.com·1d·

Discuss: Hacker News

🐘PostgreSQL Internals

Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension

semiwiki.com·1d

The Evolution of Redis: From Cache to AI-Database (V1.0 to 8.4)

percona.com·7h

🐉DragonflyDB

DiskCache: Disk Backed Cache — DiskCache 5.6.1 documentation

grantjenks.com·22h

💾Cache Design

Why AI Needs GPUs and TPUs: The Hardware Behind LLMs

blog.bytebytego.com·2d

⚡Hardware Acceleration

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