Skip to main content
Scour
Browse
Getting Started
Login
Sign Up
You are offline. Trying to reconnect...
Close
Copied to clipboard
Close
Unable to share or copy to clipboard
Close
🔁 Cache Coherence
Multi-Core, Memory Models, MESI Protocol, CPU Architecture
Filter Results
Timeframe
Fresh
Past Hour
Today
This Week
This Month
Feeds to Scour
Subscribed
All
Scoured
146401
posts in
27.4
ms
The ongoing quest for atomic
buffered
writes
lwn.net
·
4h
🚧
Memory Barriers
Utility-Based Cache
Partitioning
: Making Shared
Caches
Smarter in Multi-Core Systems
dev.to
·
3d
·
Discuss:
DEV
🧩
Cache Partitioning
Show HN:
Benchmarking
the Keep memory system with
LoCoMo
keepnotes.ai
·
9h
·
Discuss:
Hacker News
🧠
Memory Models
Rare Huawei-ByteDance alliance unveils
RRAM
AI chip delivering 66x CPU speed at
ISSCC
2026
digitimes.com
·
10h
🧠
PIM
Optimal Heterogeneous Memory Configs for AI Tasks Under
Specified
Performance Metrics (Stanford,
UCSC
)
semiengineering.com
·
1d
🧩
mimalloc
Entrpi/eemicrogpt
: The most extreme way to train a GPT in pure, dependency-free C. 1546x faster than Python. Optimized for Apple Silicon with SME2.
github.com
·
11h
·
Discuss:
Hacker News
🚀
Intel ISPC
KEEP: A
KV-Cache-Centric
Memory Management System for Efficient
Embodied
Planning
arxiv.org
·
22h
🏛️
Region-Based Memory
TurboSparse
Efficiency: Achieving 97% Parameter Sparsity in
Mixtral-47B
hackernoon.com
·
12m
🤖
TVM
Building a Virtual Computer for the Intel 80286
hackster.io
·
7h
⚡
RISC-V
Intel’s new
Xeon
600
processors
confirmed to clock up to 4.9GHz
kitguru.net
·
13h
⚙️
CPU Microarchitecture
Memory Decoding Journal Club:
Engram
cell connectivity as a mechanism for information
encoding
and memory function
lesswrong.com
·
1h
🔄
Hardware Transactional Memory
Understanding
Cache
Coherency
dev.to
·
5d
·
Discuss:
DEV
📋
Zero-Copy
Quieno/izalloc
: Drop-in, dependency-free, minimal memory allocator in C that passes 42 Shool's norm.
github.com
·
1d
·
Discuss:
r/C_Programming
🧩
Mimalloc Internals
Advancing Automotive Memory: Development of an
8nm
128Mb Embedded STT-MRAM with
Sub-ppm
Reliability
semiwiki.com
·
1d
🔄
Hardware Transactional Memory
Advancing
vRAN
Economics with AMD
EPYC
8005 Server CPUs
storagereview.com
·
10h
🛡️
AMD SEV
Zero-Waste Agentic RAG: Designing
Caching
Architectures to
Minimize
Latency and LLM Costs at Scale
towardsdatascience.com
·
1d
🎴
TAO
Memory
Caching
:
RNNs
with Growing Memory
arxiv.org
·
22h
⚡
Cache Optimization
WarpSpeed
automatically rewrites Nvidia core library, achieves 3.6-100x
speedup
doubleai.com
·
10h
·
Discuss:
Hacker News
⚡
Hardware Acceleration
The SSD cache trap: Why
NVMe
drives won't speed up your
Plex
NAS
howtogeek.com
·
1d
💽
NVMe
Mount
Mayhem
at Netflix: Scaling Containers on Modern
CPUs
netflixtechblog.com
·
2d
·
Discuss:
Hacker News
🔗
Intrusive Containers
Loading...
Loading more...
Page 2 »
Keyboard Shortcuts
Navigation
Next / previous item
j
/
k
Open post
o
or
Enter
Preview post
v
Post Actions
Love post
a
Like post
l
Dislike post
d
Undo reaction
u
Recommendations
Add interest / feed
Enter
Not interested
x
Go to
Home
g
h
Interests
g
i
Feeds
g
f
Likes
g
l
History
g
y
Changelog
g
c
Settings
g
s
Browse
g
b
Search
/
Pagination
Next page
n
Previous page
p
General
Show this help
?
Submit feedback
!
Close modal / unfocus
Esc
Press
?
anytime to show this help